The design of integrated circuits (IC) involves the study of semiconductor physics, integrated circuit processing, transistor-level design, logic-level design, system-level design, testing, and evaluation. In testing and evaluating a new IC design, the designer must have the ability to find, characterize and fix, otherwise known as debug, design-related, as well as process-related issues, that limit IC device performance or production yields. Random variations in critical IC device parameters result in performance variations that must be evaluated. The root-cause of these issues must be identified and designed out of the IC. For example, timing measurements to assess design functionality, in particular, have become a critical factor in achieving the ever-increasing challenge of reliably producing faster and faster microelectronic devices.
In the following description, reference is made to integrated circuit (IC), IC device, microelectronic die, carrier substrate, microelectronic device, and microelectronic package. An IC is an interconnected network of microcircuits which form discrete IC devices. A microelectronic die comprises a die substrate upon which microcircuits are formed. Examples of die substrates include, among others, wafers of silicon (Si), gallium arsenide (GaAs), indium phosphide (InP) and their derivatives. Various techniques are used, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic IC devices in the form of transistors, resistors, capacitors and others on the microelectronic die. The IC devices are interconnected to define specific electronic circuits that perform specific functions, such as the function of a microprocessor or a computer memory.
A microelectronic device is defined as a microelectronic die electrically interconnected with a carrier substrate. A microelectronic package is a microelectronic device that is configured as a finished package with additional components, such as electrical interconnects, a die lid, a heat dissipation device. An example of a microelectronic package includes, but is not limited to, a flip-chip ball grid array (FC-BGA) microprocessor package.
The IC design debug process is accomplished by applying a great deal of understanding and expertise in architecture and circuit design to the testing and analysis of test results to find the root-cause of marginal circuit performance. This is done using, among other things, design-for-test and design-for-debug features integrated into the IC itself, software tools and automated test equipment, and specialized diagnostic equipment which allow optical probing and time-resolved emission analysis. In general, this root-cause analysis is one of the most time-consuming tasks of the debug phase of product development and has a major impact on engineering and production tape-out schedules.
The challenge to analyze IC's increases as IC device complexity increases. To debug and validate the newest IC designs, advanced diagnostic technology is required that is sophisticated enough to analyze sub-micron sized IC devices as well as able to produce diagnostic data quickly and in a format easily understood by those not possessing extensive knowledge of the specific IC architecture of the IC being tested.
State of the art test and debugging tools such as logic analyzers, in-circuit emulators, and microprocessor development systems, and those already discussed, do not satisfy this need completely. These tools suffer from limitations which include poor IC device resolution, extensive labor and time to perform and analyze, and require that the test and evaluation of the diagnostic data be performed by those having expertise in architecture and circuit design. Additionally, these tools are limited in their ability to diagnose individual IC devices when the microelectronic die is packaged and integrated with a carrier substrate. In FC-BGA and FC-PGA packages, for example, only the back-side of the microelectronic die is exposed once interconnected with the carrier substrate, precluding direct access to the IC devices via the die interconnect pads.
The essence of the problem to be addressed is to provide a non-destructive and repeatable evaluation of IC devices, individually as well as a part of a complex circuit. This evaluation should assist in the design process to identify those IC devices or the design of the circuit comprising a group of IC devices that are hindering the goal of meeting all of the desired performance requirements of the microelectronic die and package. These performance requirements are specifiable in terms of circuit speed, noise immunity, and chip area, among others.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for methods that provide IC evaluation to identify those IC devices and/or combination of IC devices in a particular circuit path that are limiting the overall performance of the microelectronic die. Additionally, there is a need for methods to enable those without design expertise to acquire relevant data which is easily identifiable as meeting a pass/fail threshold. The methods must address the need to meet the challenge of both package level and die level evaluation of deep-submicron IC devices. Further, the methods need to provide non-destructive, repeatable, high bandwidth evaluation of the IC in which only the backside of the microelectronic die is accessible, such as the case wherein the die is assembled into a microelectronic package.